View PT9250_4533849.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PT9250 48-channel Single Chip GPS Receiver
DESCRIPTION
The PT9250 is an advanced single chip GPS receiver to integrate baseband, RF and flash memory into the 7mm x 10mm package making for an extremely compact design. This advanced solution offers best-in-class acquisition & tracking sensitivity, TTFF and accuracy. The PT9250 architecture uses an FFT and Matched Filter that delivers performance equivalent to more than 75,000 correlators. This represents a quantum leap forward in GPS performance. The PT9250's architecture enables unmatched TTFF at low signal levels. The PT9250 includes a powerful GPS DSP integrated with a 32-bit RISC microprocessor, 1Mb of SRAM and 4Mb flash memory. The PT9250 also integrates a built-in low power RTC circuit for low power operation and battery backup RAM for satellite information. PTC supports full reference design, demonstration system, software evaluation tools and other supporting documentation.
FEATURES
Reception frequency: 1575.42MHz (L1 band, CA code) Reception frequency: 1575.42MHz (L1 band, CA code) Reference clock (TCXO) frequency: 16.368MHz or 16.369MHz Best-in-class acquisition and tracking sensitivity, TTFF and accuracy. - Tracking sensitivity -159dBm - Acquisition sensitivity -143dBm SoC to integrate major RF receiver, digital baseband and flash memory 48 channel acquisition and tracking engine 32 bits RISC CPU (MIPS) Internal low power real time clock Battery back-up SRAM 2-channel UART communication port SPI host interface 2 external interrupts Watch dog timer support 16 GPIOs 1 PPS output Support NMEA-0183(V3.01) 140 balls LFBGA Temperature range: -40/+85
APPLICATIONS
GPS receivers Vehicle navigator Cellular phone PDA PMP
BLOCK DIAGRAM
Tel: 886-66296288Fax: 886-29174598 http://www.princeton.com.tw2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT9250
APPLICATION CIRCUITS
V1.2
2
PT9250
ORDER INFORMATION
Valid Part Number PT9250 Package Type 10mmx7mm LFBGA Top Code PT9250
BALL CONFIGURATION
A1 E_A15 B1 A2 A3 A4 A5 A6 A7 GPIO4 B7 GPIO1 C7 GPIO0 D7 GPIO7 E7 E_D11 F7 VSS_F G7 VDD_IO H7 A8 GPIO2 B8 E_D14 C8 E_D6 D8 E_D12 E8 E_D9 F8 E_D0 G8 E_CS_n H8 VDD_K J8 CFG3 K8 A9 E_BYTE B9 E_D7 C9 E_D5 D9 VSS_F E9 E_D10 F9 E_D8 G9 E_A0 H9 VDD_K J9 VSS_K K9 A10 E_A16 B10 E_D15 C10 E_D13 D10 E_D4 E10 VDD_F F10 E_D3 G10 E_D1 H10 E_OE_n J10 VSS_K K10 REG_EN RTC_VDD RTC_XI B2 B3 E_A14 C3 E_A13 D3 E_A10 E3 E_WR_n F3 E_A6 G3 E_A4 H3 E_A2 J3 B4 GPIO11 C4 GPIO10 D4 VDD_K E4 VDD_K F4 VSS_IO G4 E_A7 H4 E_A3 J4 VSS_IO K4 RTC_XO RTC_VSS B5 GPIO9 C5 GPIO8 D5 VSS_IO E5 B6 GPIO6 C6 GPIO5 D6 GPIO3 E6
REG_VDD REG_VSS C1 REG_1V2 D1 E_A12 E1 E_A9 F1 E_RP G1 E_A17 H1 PLLTKO J1 C2 VDEC D2 E_A11 E2 E_A8 F2 E_RYBY G2 E_A5 H2 E_A1 J2
VDD_IO VDD_IO F5 VSS_K G5 VDD_IO H5 F6 VDD_IO G6 E_D2 H6
GND_IO SYS_RST_n VDD_IO J5 VSS_IO K5 J6 VSS_K K6 J7 GPIO15 K7
AVDD_PLL AVSS_PLL VSS_IO K1 RFXO L1 RFXI M1 AON N1 PVDD P1 NC K2 K3
ICE_CLK ICE_TMS ICE_TDO ICE_TDI ICE_RST_nAFE_CLK AFE_MAG AFE_SGN GPIO12 L2 MODE0 M2 RFPLL N2 ISNS P2 LNI L3 MODE1 M3 VB N3 RFGND P3 AVDD L4 RFXEN M4 L5 DVSS M5 L6 RF_GND M6 DVDD N6 L7 CP M7 AOK N7 L8 MAG M8 AGCCAP N8 NC P8 IF1N L9 SGN M9 P0 N9 P1 P9 IF2P L10 GPIO13 M10 GPIO14 N10 IF2N P10 NC
RF_GND RF_GND N4 N5
RF_GND RF_GND RF_GND RF_MODE P4 LNO P5 RFIN P6 VBG P7 IF1P
V1.2
3
PT9250
BALL DESCRIPTION
Ball Name RF Interface SGN MAG AOK CP RFXEN RFXI RFXO VB RFPLL AON LNI ISNS PVDD LNO RFIN VBG IF1P IF1N RFMODE AGCCAP P1 P0 RF Power Pins DVSS DVDD AVDD RF_GND Flash Interface E_D0 ~ E_D15 E_A0 ~ E_A17 E_CS_n E_WR_n E_OE_n E_BYTE E_RP E_RYBY RF Chip Interface AFE_CLK AFE_SGN AFE_MAG CPU Peripheral GPIO15(OPPS) GPIO14 GPIO13 GPIO12 GPIO11 (UATX1) GPIO10 (UARX1) GPIO9 (UATX0) GPIO8 (UARX0) V1.2 I/O Type O O O I/O I I O O O O I I O O I O O O I I/O I I G P P G I/O O O O O I I O I I I I/O I/O I/O I/O I/O I/O I/O I/O Description Quantized 2nd IF "sign" bit Quantized 2nd IF "magnitude" bit Active antenna status output (AOK = HIGH = active antenna OK; AOK=LOW=active antenna either open or shorted) Reference clock input/output Crystal oscillator enable pin (XEN=HIGH=enabled; XEN=LOW=disabled) Crystal oscillator input Crystal oscillator output Regulator (1.9V) output Charge pump output Antenna switch-controlled supply voltage to active antenna LNA input Antenna detector current sense input Supply voltage (active antenna) LNA output Mixer input Band gap reference (1.23V) output Differential first-stage IF amplifier output/differential IF AGC input Reference frequency mode select input AGC capacitor connection. Sets the AGC time constant. Power-down control pins Ground (digital circuitry) Supply voltage (digital circuitry) Supply voltage (analog circuitry) Ground (analog circuitry) External Data bus bit 0 ~ 15 External Address bus bit 0 ~ 17 External memory chip select, active low External memory write signal, active low External memory output enable, active low Byte mode Reset of external memory Ready / Busy output RF chip clock input RF chip sign data bit RF chip magnitude data bit GPIO15 / One pulse per-second GPIO14 GPIO13 GPIO12 GPIO11 / UART 1 transmission data GPIO10 / UART 1 receive data GPIO9 / UART 0 transmission data GPIO8 / UART 0 receive data 4
PT9250
Ball Name I/O Type Description GPIO7(EXT_INT1) I/O GPIO7 / External interrupt input GPIO6(EXT_INT0) I/O GPIO6 / External interrupt input GPIO5 I/O GPIO5 GPIO4 I/O GPIO4 GPIO3 (CSIO_RDY) I/O GPIO3 / CSIO ready GPIO2 (CSIO_CLK) I/O GPIO2 / CSIO clock GPIO1 (CSIO_DO) I/O GPIO1 / CSIO data output GPIO0 (CSIO_DI) I/O GPIO0 / CSIO data input ICE Interface ICE_CLK I ICE clock ICE_TMS I ICE mode select ICE_RST_n I ICE reset, active low. ICE_TDI I ICE data input ICE_TDO O ICE data output System Interface SYS_RST_n I System reset, active low MODE0, MODE1 I Test mode selection, pull low CFG0,CFG1,CFG3 I Configuration, pull low. RTC_XO O RTC crystal clock output RTC_XI I RTC crystal clock input PLLTKO O PLL test clock output Regulator REG_EN I Regulator enable REG_1V2 O Regulator 1.2V output VDEC I Voltage detect Baseband Power Pins VDD_REG P 3.3V power supply for regulator VSS_REG G Ground for regulator AVDD_PLL P Analog 1.2V power supply for PLL circuit AVSS_PLL G Analog Ground for PLL VDD_RTC P 1.2V power supply for RTC VSS_RTC G Ground for RTC VDD_IO P 3.3V power supply for IO VSS_IO G Ground for IO VDD_K P 1.2V power for internal logic core VSS_K G Ground for internal logic VDD_F P 3.3V power supply for flash VSS_F G Ground for flash NC Open IO Types I Input(3.3V CMOS level) O Output (3.3V CMOS level) IO Bi-direction IO(3.3V CMOS level) P Power G Ground
V1.2
5
PT9250 IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw
V1.2
6
PT9250
V1.2
7

▲Up To Search▲

Price & Availability of PT9250

	To Download PT9250 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .